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1 ? fn8221.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x98027 275mhz triple video digitizer with digital pll the x98027 3-channel, 8-bit analog front end (afe) contains all the components necessary to digitize analog rgb or yuv graphics signals from personal computers, workstations and video set-top boxes. the fully differential analog design provides high psrr and dynamic performance to meet the stri ngent requirements of the graphics display industry. the afe?s 275msps conversion rate supports resolutions up to qxga at 60hz refresh rate, while the front end's high input bandwidth ensures sharp images at the highest resolutions. to minimize noise, the x98027 's analog section features 2 sets of pseudo-differential rgb inputs with programmable input bandwidth, as well as internal dc restore clamping (including mid-scale clamping for yuv signals). this is followed by the programmable gain/offset stage and the three 275msps analog- to-digital converters (adcs). automatic black level compensation (ablc? ) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. the x98027's digital pll generates a pixel clock from the analog source's hsync or sog (sync-on-green) signals. pixel clock output frequencies range from 10mhz to 275mhz with sampling clock jitter of 250ps peak to peak. features ? 275msps maximum conversion rate ? low pll clock jitter (250ps p-p @ 275msps) ? 64 interpixel sampling positions ? 0.35v p-p to 1.4v p-p video input range ? programmable bandwidth (100mhz to 780mhz) ? 2 channel input multiplexer ? rgb and yuv 4:2:2 output formats ? 5 embedded voltage regulators allow operation from single 3.3v supply and enhance performance, isolation ? completely independent 8 bit gain/10 bit offset control ? csync and sog support ? trilevel sync detection ? 1.2w typical p d @ 275msps ? pb-free plus anneal available (rohs compliant) applications ? lcd monitors and projectors ? digital tvs ? plasma display panels ? rgb graphics processing ? scan converters simplified block diagram rgb/ypbpr in 1 pga 8 bit adc offset dac ablc? 8 or 16 x3 sog in 1/2 hsync in 1/2 vsync in 1/2 sync processing digital pll voltage clamp rgb/ypbpr in 2 3 3 rgb/yuv out pixelclk out hs out hsync out afe configuration and control vsync out + data sheet may 26, 2005
2 fn8221.0 may 26, 2005 block diagram ordering information part number maximum pixel rate temp range (c) package part marking x98027l128-3.3 275mhz 0 to 70 128 mqfp x98027l-3.3 x98027l128-3.3-z (see note) 275mhz 0 to 70 128 mqfp (pb-free) x98027l-3.3z note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. g in 1 rgb gnd 1 g in 2 rgb gnd 2 v in + v in - pga 8 bit adc + v clamp r in 1 r in 2 v in + v in - pga 8 bit adc + v clamp b in 1 b in 2 v in + v in - pga 8 bit adc + v clamp offset dac offset dac offset dac ablc? ablc? ablc? 8 10 8 10 8 10 8 b s [7:0] 8 b p [7:0] 8 g s [7:0] 8 g p [7:0] 8 r s [7:0] 8 r p [7:0] sog in 1 sog in 2 hsync in 1 hsync in 2 vsync in 1 vsync in 2 clockinv xtal in xtal out scl sda saddr sync processing digital pll afe configuration and control dataclk dataclk hs out vs out serial interface output data formatter hsync out vsync out xtalclk out x98027
3 fn8221.0 may 26, 2005 t absolute maximum ratings recommended operating conditions voltage on v a , v d , or v x (referenced to gnd a =gnd d =gnd x ) . . . . . . . . . . . . . . . . . . . 4.0v voltage on any analog input pin (referenced to gnd a ) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v a voltage on any digital input pin (referenced to gnd d ) . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma operating temperature range . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c temperature (commercial) . . . . . . . . . . . . . . . . . . . . . 0c to +70c supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . v a = v d = v x = 3.3v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. electrical specifications specifications apply for v a = v d = v x = 3.3v, pixel rate = 275mhz, f xtal = 25mhz, t a = 25c, unless otherwise noted symbol parameter comment min typ max unit full channel characteristics adc resolution 8bits missing codes guaranteed monotonic none conversion rate per channel 10 275 mhz dnl differential non-linearity 0.7 +1.2 -0.9 lsb inl integral non-linearity 1.6 3.75 lsb gain adjustment range 6 db gain adjustment resolution 8bits gain matching between channels percent of full scale 1 % full channel offset error, ablc? enabled adc l sbs, over time and temperature 0.125 0.5 lsb offset adjustment range, ablc? enabled or disabled adc lsbs (see ablc? applications information section) 127 lsb overvoltage recovery time for 150% overrange, maximum bandwidth setting 5ns analog video input characteristics (r in 1, g in 1, b in 1, r in 2, g in 2, b in 2) input range 0.35 0.7 1.4 v p-p input bias current dc restore clamp off 0.01 1 a input capacitance 5pf full power bandwidth programmable 780 mhz input characteristics (sog in 1, sog in 2) v ih /v il input threshold voltage programmable - see register listing for details 0 to -0.3 v hysteresis centered around threshold voltage 40 mv input capacitance 5pf input characteristics (hsync in 1, hsync in 2) v ih /v il input threshold voltage programmable - see register listing for details 0.4 to 3.2 v hysteresis centered around threshold voltage 240 mv r in input impedance 1.2 k input capacitance 5pf x98027
4 fn8221.0 may 26, 2005 digital input characteristics (sda, saddr, clockinv in , reset ) v ih input high voltage 2.0 v v il input low voltage 0.8 v i input leakage current reset has a 70k pullup to v d 10 na input capacitance 5pf schmitt digital input characteristics (scl, vsync in 1, vsync in 2) v t + low to high threshold voltage 1.45 v v t - high to low threshold voltage 0.95 v i input leakage current 10 na input capacitance 5pf digital output characteristics (dataclk, dataclk ) v oh output high voltage, i o = 16ma 2.4 v v ol output low voltage, i o = -16ma 0.4 v digital output characteristics (r p , g p , b p , r s , g s , b s , hs out , vs out , hsync out , vsync out ) v oh output high voltage, i o = 8ma 2.4 v v ol output low voltage, i o = -8ma 0.4 v r tri pulldown to gnd d when three-state r p , g p , b p , r s , g s , b s only 58 k digital output characteristics (sda, xtalclk out ) v oh output high voltage, i o = 4ma xtalclk out only; sda is open-drain 2.4 v v ol output low voltage, i o = -4ma 0.4 v power supply requirements v a analog supply voltage 3 3.3 3.6 v v d digital supply voltage 3 3.3 3.6 v v x crystal oscillator supply voltage 3 3.3 3.6 v i a analog supply current operating 190 200 ma i d digital supply current operating (grayscale) 170 180 ma i x crystal oscillator supply current 0.7 2 ma p d total power dissipation operating (average) 1.2 1.4 w power-down mode 50 80 mw ja thermal resistance, junction to ambient 30 c/w ac timing characteristics pll jitter 250 450 ps p-p sampling phase steps 5.6 per step 64 sampling phase tempco 1 ps/c sampling phase differential nonlinearity degrees out of 360 3 hsync frequency range 10 150 khz f xtal crystal frequency range 23 (note 2) 25 27 mhz t setup data valid before rising edge of dataclk 15pf dataclk load, 15pf data load (note 1) 1.3 ns electrical specifications specifications apply for v a = v d = v x = 3.3v, pixel rate = 275mhz, f xtal = 25mhz, t a = 25c, unless otherwise noted (continued) symbol parameter comment min typ max unit x98027
5 fn8221.0 may 26, 2005 t hold data valid after rising edge of dataclk 15pf dataclk load, 15pf data load (note 1) 2.0 ns ac timing characteristics (2 wire interface) f scl scl clock frequency 0 400 khz maximum width of a glitch on scl that will be suppressed 2 xtal periods min 80 ns t aa scl low to sda data out valid 5 xtal periods plus sda?s rc time constant see comment s t buf time the bus must be free before a new transmission can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0ns t su:sto stop condition setup time 0.6 s t dh data output hold time 4 xtal periods min 160 ns notes: 1. setup and hold times are at a 140mhz dataclk rate. 2. see table 8 on page 24. electrical specifications specifications apply for v a = v d = v x = 3.3v, pixel rate = 275mhz, f xtal = 25mhz, t a = 25c, unless otherwise noted (continued) symbol parameter comment min typ max unit t su:sto t dh t high t su:st t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r figure 1. 2 wire interface timing dataclk t setup t hold dataclk pixel data figure 2. data output setup and hold timing x98027
6 fn8221.0 may 26, 2005 th hsync d ( bl l di t ili ) th t th dpll i l k d t programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 d 0 r p /g p /b p [7:0] hs out 8.5 dataclk pipeline latency r s /g s /b s [7:0] p 10 p 11 p 12 d 1 d 2 d 3 hsync in the hsync edge (programmable leading or trailing) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk t hsyncin-to-hsout = 7.5ns + (phase/64 +8.5)*t pixel figure 3. 24 bit output mode programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 hs out 8.5 dataclk pipeline latency p 10 p 11 p 12 hsync in the hsync edge (programmable leading or trailing) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk g 0 (y o ) g 1 (y 1 )g 2 (y 2 ) b 0 (u o )r 1 (v 1 )b 2 (u 2 ) g p [7:0] r p [7:0] b p [7:0] t hsyncin-to-hsout = 7.5ns + (phase/64 +8.5)*t pixel figure 4. 24 bit 4:2:2 output mode (for yuv signals) x98027
7 fn8221.0 may 26, 2005 t hsyncin-to-hsout = 7.5ns + (phase/64 +10.5)*t pixel d 1 d 3 programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 d 0 r p /g p /b p [7:0] hs out p 10 p 11 p 12 d 2 the hsync edge (programmable leading or trailing) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk r s /g s /b s [7:0] hsync in the hsync ed g e (p ro g rammable leadin g or trailin g) that the dpll is locked to. hsync figure 5. 48 bit output mode programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 hs out p 10 p 11 the hsync edge (programmable leading or tra iling) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk hsync in d 0 r p /g p /b p [7:0] d 2 d 1 r s /g s /b s [7:0] t hsyncin-to-hsout = 7.5ns + (phase/64 +8.5)*t pixel figure 6. 48 bit output mode, interleaved timing x98027
8 fn8221.0 may 26, 2005 pinout x98027 (128-pin mqfp) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 nc nc gnd a v bypass gnd a v a r in 1 gnd a v bypass gnd a v a g in 1 rgb gnd 1 sog in 1 gnd a v bypass gnd a v a b in 1 v a gnd a r in 2 gnd a g in 2 rgb gnd 2 sog in 2 gnd a b in 2 v a gnd a v coreadc gnd d hs ync in 1 hs ync in 2 v a gnd a gnd x v x r s 5 r s 6 r s 7 v d gnd d g p 0 g p 1 g p 2 g p 3 g p 4 g p 5 g p 6 g p 7 v d gnd d g s 0 g s 1 g s 2 g s 3 g s 4 g s 5 g s 6 g s 7 v core gnd d v d gnd d b p 0 b p 1 b p 2 b p 3 b p 4 b p 5 b p 6 b p 7 v d gnd d vreg in 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 vsync out hs ync out vs out hs out v d gnd d dataclk dataclk gnd d r p 0 r p 1 r p 2 r p 3 r p 4 r p 5 r p 6 r p 7 v d gnd d v core gnd d r s 0 r s 1 r s 2 r s 3 r s 4 xtal in xtal out clockinv in v pll gnd d vsync in 1 vsync in 2 reset xtalclock out s addr sda scl gnd d v core gnd d v d b s 7 b s 6 b s 5 b s 4 b s 3 b s 2 b s 1 b s 0 nc vreg out x98027
9 fn8221.0 may 26, 2005 pin descriptions symbol pin description r in 1 7 analog input. red channel 1. dc couple or ac couple through 0.1f. g in 1 12 analog input. green channel 1. dc couple or ac couple through 0.1f. b in 1 19 analog input. blue channel 1. dc couple or ac couple through 0.1f. rgb gnd 1 13 analog input. ground reference for the r, g, and b i nputs of channel 1 in the dc coupled configuration. connect to the same ground as channel 1's r, g, and b term ination resistors. this signal is not used in the ac-coupled configuration, but the pin should still be tied to gnd a . sog in 1 14 analog input. sync on green. connect to g in 1 through a 0.01f capacitor in series with a 500 resistor. hsync in 1 33 digital input, 5v tolerant, 240mv hysteresis, 1.2k impedance to gnd a . connect to channel 1's hsync signal through a 680 series resistor. vsync in 1 44 digital input, 5v tolerant, 500mv hyst eresis. connect to c hannel 1's vsync signal. r in 2 22 analog input. red channel 2. dc couple or ac couple through 0.1f. g in 2 24 analog input. green channel 2. dc couple or ac couple through 0.1f. b in 2 28 analog input. blue channel 2. dc couple or ac couple through 0.1f. rgb gnd 2 25 analog input. ground reference for the r, g, and b i nputs of channel 2 in the dc coupled configuration. connect to the same ground as channel 1's r, g, and b term ination resistors. this signal is not used in the ac-coupled configuration, but the pin should still be tied to gnd a . sog in 2 26 analog input. sync on green. connect to g in 1 through a 0.01f capacitor in series with a 500 resistor. hsync in 2 34 digital input, 5v tolerant, 240mv hysteresis, 1.2k impedance to gnd a . connect to channel 2's hsync signal through a 680 series resistor. vsync in 2 45 digital input, 5v tolerant, 500mv hyst eresis. connect to c hannel 2's vsync signal. clockinv in 41 digital input, 5v tolerant. when high, changes the pixel sampling phase by 180 degrees. toggle at frame rate during vsync to allow 2x undersampling to sa mple odd and even pixels on sequential frames. tie to d gnd if unused. reset 46 digital input, 5v tolerant, active low, 70k pull-up to v d . take low for at least 1s and then high again to reset the x98027. this pin is not necessary for normal use and may be tied directly to the v d supply. xtal in 39 analog input. connect to external 23mhz to 27mhz crystal and load capacitor (see crystal spec for recommended loading). typical o scillation amplitude is 1.0v p-p centered around 0.5v. xtal out 40 analog output. connect to external 23mhz to 27mhz crystal and load capacitor (see crystal spec for recommended loading). typical o scillation amplitude is 1.0v p-p centered around 0.5v. xtalclk out 47 3.3v digital output. buffered crystal clock output at f xtal or f xtal /2. may be used as system clock for other system components. saddr 48 digital input, 5v tolerant. address = 0x4c (0x98 including r/w bit) when tied low. address = 0x4d (0x9a including r/w bit) when tied high. scl 50 digital input, 5v tolerant, 500mv hysteresis . serial data clock for 2-wire interface. sda 49 bidirectional digital i/o, open drain, 5v to lerant. serial data i/o for 2-wire interface. r p [7:0] 112-119 3.3v digital output. red channel, primar y pixel data. 58k pulldown when three-stated. r s [7:0] 100-107 3.3v digital output. red channel, secondary pixel data. 58k pulldown when three-stated. g p [7:0] 90-97 3.3v digital output. green channel, primar y pixel data. 58k pulldown when three-stated. g s [7:0] 80-87 3.3v digital output. green channel, secondary pixel data. 58k pulldown when three-stated. b p [7:0] 68-75 3.3v digital output. blue channel, primary pixel data. 58k pulldown when three-stated. b s [7:0] 55-62 3.3v digital output. blue channel, sec ondary pixel data. 58k pulldown when three-stated. dataclk 121 3.3v digital output. data clock output. equal to pi xel clock rate in 24 bit mode, one half pixel clock rate in 48 bit mode. dataclk 122 3.3v digital output. inverse of dataclk. x98027
10 fn8221.0 may 26, 2005 hs out 125 3.3v digital output. hsync output aligned with pixel data. use this output to frame the digital output data. this output is always purely horizontal sync (without any composite sync signals) vs out 126 3.3v digital output.artificial vsync output aligned with pixel data. vsync is generated 8 pixel clocks after the trailing edge of hs out . this signal is usually not needed - use vsync out as vsync source. hsync out 127 3.3v digital output. buffered hsync (or sog or csyn c) output. this is typically used to measure hsync period. hs out should be used to detect the beginning of a line. this output will pass composite sync signals and macrovision signals if present on hsync in or sog in . vsync out 128 3.3v digital output. buffered vsync output. for composit e sync signals, this output will be asserted for the duration of the disruption of the normal hsync pattern. this is typically used to detect the beginning of a frame and measure the vsync period. v a 6, 11, 18, 20, 29, 35 power supply for the analog section. connect to a 3.3v supply and bypass each pin to gnd a with 0.1f. gnd a 3, 5, 8, 10, 15, 17, 21, 23, 27, 30, 36 ground return for v a and v bypass . v d 54, 67, 77, 89, 99, 111, 124 power supply for all digital i/os. connect to a 3.3v supply and bypass each pin to gnd d with 0.1f. gnd d 32, 43, 51, 53, 66, 76, 78, 88, 98, 108, 110, 120, 123 ground return for v d , v core , v coreadc , and v pll . v x 38 power supply for crystal oscillator. connect to a 3.3v supply and bypass to gnd x with 0.1f. gnd x 37 ground return for v x . v bypass 4, 9, 16 bypass these pins to gnd a with 0.1f. do not connect these pins to each other or anything else. vreg in 65 3.3v input voltage for v core voltage regulator. connect to a 3.3v source, and bypass to gnd d with 0.1f. vreg out 64 regulated output voltage for v pll , v coreadc and v core ; typically 1.9v. connect only to v pll , v coreadc and v core and bypass at input pins as instructed below. do not connect to anything else - this output can only supply power to v pll , v coreadc and v core . v coreadc 31 internal power for the adc?s digital logic. connect to vreg out through a 10 resistor and bypass to gnd d with 0.1f. v pll 42 internal power for the pll?s digital logic. connect to vreg out through a 10 resistor and bypass to gnd d with 0.1f. v core 52, 79, 109 internal power for core logic. connect to vreg out and bypass each pin to gnd d with 0.1f. nc 1, 2, 63 reserved. do not connect anything to these pins. pin descriptions (continued) symbol pin description x98027
11 fn8221.0 may 26, 2005 register listing address register (default value) bit(s) function name description 0x01 sync status (read only) 0 hsync1 active 0: hsync1 is inactive 1: hsync1 is active 1 hsync2 active 0: hsync2 is inactive 1: hsync2 is active 2 vsync1 active 0: vsync1 is inactive 1: vsync1 is active 3 vsync2 active 0: vsync2 is inactive 1: vsync2 is active 4 sog1 active 0: sog1 is inactive 1: sog1 is active 5 sog2 active 0: sog2 is inactive 1: sog2 is active 6 pll locked 0: pll is unlocked 1: pll is locked to incoming hsync 7 csync detected at sync splitter output 0: composite sync signal not detected 1: composite sync signal is detected 0x02 sync polarity (read only) 0 hsync1 polarity 0: hsync1 is active high 1: hsync1 is active low 1 hsync2 polarity 0: hsync2 is active high 1: hsync2 is active low 2vsync1 polarity 0: vsync1 is active high 1: vsync1 is active low 3vsync2 polarity 0: vsync2 is active high 1: vsync2 is active low 4 hsync1 trilevel 0: hsync1 is standard sync 1: hsync1 is trilevel sync 5 hsync2 trilevel 0: hsync2 is standard sync 1: hsync2 is trilevel sync 7:6 n/a returns 0 0x03 hsync slicer (0x44) 2:0 hsync1 threshold 000 = lowest (0.4v) all values referred to 100 = default (2.0v) voltage at hsync input 111 = highest (3.2v) pin, 240mv hysteresis 3 reserved set to 00 6:4 hsync2 threshold see hsync1 7 disable glitch filter 0: hsync/vsync digital glitch filter enabled (default) 1: hsync/vsync digital glitch filter disabled 0x04 sog slicer (0x08) 3:0 sog1 and sog2 threshold 0x0 = lowest (0mv) 40mv hysteresis at 0x8 = default (160mv) all settings 0xf = highest (300mv) 20mv step size 4 sog filter enable 0: sog low pass filter disabled (default) 1: sog low pass filter enabled, 14mhz corner 5sog hysteresis disable 0: 40mv sog hysteresis enabled 1: 40mv sog hysteresis disabled (default) 7:6 reserved set to 00. x98027
12 fn8221.0 may 26, 2005 0x05 input configuration (0x00) 0 channel select 0: vga1 1: vga2 1 input coupling 0: ac coupled (positive input connected to clamp dac during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp dac) 1: dc coupled (+ and - inputs are brought to pads and never connected to clamp dacs). analog clamp signal is turned off in this mode. 2 rgb/yuv 0: rgb inputs (clamp dac = 300mv for r, g, b, half scale analog shift for r, g, and b, base ablc? target code = 0x00 for r, g, and b) 1: yuv inputs (clamp dac = 600mv for r and b, 300mv for g, half scale analog shift for g channel only, base ablc? target code = 0x00 for g, = 0x80 for r and b) 3 sync type 0: separate hsync/vsync 1: composite (from sog or csync on hsync) 4 composite sync source 0: sog in 1: hsync in note: if sync type = 0, the multiplexer will pass hsync in regardless of the state of this bit. 5 coast clamp enable 0: dc restore clamping and ablc? suspended during coast 1: dc restore clamping and ablc? continue during coast 7:6 reserved set to 00. 0x06 red gain (0x55) 7:0 red gain channel gain, where: gain (v/v) = 0.5 + [7:0]/170 0x00: gain = 0.5 v/v (1.4vp-p input = full range of adc) 0x55: gain = 1.0 v/v (0.7vp-p input = full range of adc) 0xff: gain = 2.0 v/v (0.35vp-p input = full range of adc) 0x07 green gain (0x55) 7:0 green gain 0x08 blue gain (0x55) 7:0 blue gain 0x09 red offset (0x80) 7:0 red offset ablc? enabled: digital offset control. a 1 lsb change in this register will shift the adc output by 1 lsb. ablc? disabled: analog offset control. these bits go to the upper 8 bits of the 10 bit offset dac. a 1lsb change in this register will shift the adc out put approximately 1 lsb (offset dac range = 0) or 0.5lsbs (offset dac range = 1). 0x00 = min dac value or -0x80 digital offset, 0x80 = mid dac value or 0x00 digital offset, 0xff = max dac value or +0x7f digital offset 0x0a green offset (0x80) 7:0 green offset 0x0b blue offset (0x80) 7:0 blue offset 0x0c offset dac configuration (0x00) 0 offset dac ra nge 0: 1/2 adc fullscale (1 dac lsb ~ 1 adc lsb) 1: 1/4 adc fullscale (1 dac lsb ~ 1/2 adc lsb) 1 reserved set to 0. 3:2 red offset dac lsbs these bits are the lsbs necessary for 10 bit manual offset dac control. combine with their respective msbs in registers 0x09, 0x0a, and 0x0b to achieve 10 bi t offset dac control. 5:4 green offset dac lsbs 7:6 blue offset dac lsbs register listing (continued) address register (default value) bit(s) function name description x98027
13 fn8221.0 may 26, 2005 0x0d afe bandwidth (0x0e) 0 unused value doesn?t matter 3:1 afe bw 3db point for afe lowpass filter 000: 100mhz 111: 780mhz (default) 7:4 peaking 0000: disabled (default) see bandwidth and peaking control section for more information 0x0e pll htotal msb (0x03) 5:0 pll htotal msb 14 bit htotal (number of active pixels) value the minimum htotal value supported is 0x200. htotal to pll is updated on lsb write only. 0x0f pll htotal lsb (0x20) 7:0 pll htotal lsb 0x10 pll sampling phase (0x00) 5:0 pll sampling phase used to control the phase of the adc?s sample point relative to the period of a pixel. adjust to obtain optimum image quality. one step = 5.625 (1.56% of pixel period). 0x11 pll pre-coast (0x08) 7:0 pre-coast number of li nes the pll will coast prior to the start of vsync. applies only to internally generated coast signals. 0x12 pll post-coast (0x00) 7:0 post-coast number of lines the pll will coast after the end of vsync. applies only to internally generated coast signals. 0x13 pll misc (0x00) 0 pll lock edge hsync1 0: lock on trailing edge of hsync1 (default) 1: lock on leading edge of hsync1 1 pll lock edge hsync2 0: lock on trailing edge of hsync2 (default) 1: lock on leading edge of hsync2 2 reserved set to 0. 3clkinv in pin disable 0: clkinv in pin enabled (default) 1: clkinv in pin disabled (internally forced low) 5:4 clkinv in pin function 00: clkinv (default) 01: external clamp (see note) 10: external coast 11: external pixclk note: the clamp pulse is used to - perform a dc restore (if enabled) - start the ablc? function (if enabled), and - update the data to the offset dacs (always). when in the default internal clamp mode, the x98027 automatically generates the clamp pulse. if external clamp is selected, the offset dac values will only change on the leading edge of clamp. if there is no internal clamp signal, there will be up to a 100ms delay between when the pga gain or offset dac register is written to, and when the pga or offset dac is actually updated. 6 xtalclkout frequency 0: xtalclk out = f crystal (default) 1: xtalclk out = f crystal /2 7 disable xtalclkout 0 = xtalclk out enabled 1 = xtalclk out is logic low 0x14 dc restore and ablc? starting pixel msb (0x00) 4:0 dc restore and ablc? starting pixel (msb) pixel after hsync in trailing edge to begin dc restore and ablc? functions. 13 bits. set this register to the first stable black pixel following the trailing edge of hsync in . 0x15 dc restore and ablc? starting pixel lsb (0x00) 7:0 dc restore and ablc? starting pixel (lsb) 0x16 dc restore clamp width (0x10) 7:0 dc restore clamp width (pixels) width of dc restore clamp used in ac-coupled configurations. has no effect on ablc?. minimum value is 0x02 (a setting of 0x01 or 0x00 will not generate a clamp pulse). register listing (continued) address register (default value) bit(s) function name description x98027
14 fn8221.0 may 26, 2005 0x17 ablc? configuration (0x40) 0 ablc? disable 0: ablc? enabled (default) 1: ablc? disabled 1 reserved set to 0. 3:2 ablc? pixel width number of bla ck pixels averaged every line for ablc? function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels 6:4 ablc? bandwidth ablc? time constant (lines) = 2 (5+[6:4]) 000 = 32 lines 100 = 256 lines (default) 111 = 4096 lines 7 reserved set to 0. 0x18 output format (0x00) 0 bus width 0: 24 bits: data output on r p , g p , b p only; r s , g s , b s are all driven low (default) 1: 48 bits: data output on r p , g p , b p , r s , g s , b s 1 interleaving (48 bit mode only) 0: no interleaving: data changes on same edge of dataclk (default) 1: interleaved: secondary databus data changes on opposite edge of dataclk from primary databus 2bus swap (48 bit mode only) 0: first data byte after trailing edge of hsout appears on r p , g p , b p (default) 1: first data byte after trailing edge of hsout appears on r s , g s , b s (primary and secondary busses are reversed) 3 reserved set to 0. 4 422 (24 bit mode only) 0: data is formatted as 4:4:4 (rgb, default) 1: data is decimated to 4:2:2 (yuv), blue channel is driven low 5dataclk polarity 0: hs out , vs out , and pixel data change on falling edge of dataclk (default) 1: hs out , vs out , and pixel data change on rising edge of dataclk 6 vsout polarity 0: active high (default) 1: active low 7 hsout polarity 0: active high (default) 1: active low 0x19 hsout width (0x10) 7:0 hsout width hsout widt h, in pixels. minimum value is 0x01 for 24 bit modes, 0x02 for 48 bit modes. 0x1a output signal disable (0x00) 0 three-state r p [7:0] 0 = output byte enabled 1 = output byte three-stated these bits override all other i/o settings output data pins have 58k pulldown resistors to gnd d . 1 three-state r s [7:0] 2 three-state g p [7:0] 3 three-state g s [7:0] 4 three-state b p [7:0] 5 three-state b s [7:0] 6 three-state dataclk 0 = dataclk enabled 1 = dataclk three-stated 7 three-state dataclk 0 = dataclk enabled 1 = dataclk three-stated register listing (continued) address register (default value) bit(s) function name description x98027
15 fn8221.0 may 26, 2005 technical highlights the x98027 provides all the features of traditional triple channel video afes, but adds several next-generation enhancements, bringing performance and ease of use to new levels. dpll all video afes must phase lock to an hsync signal, supplied either directly or embedded in the video stream (sync on green). historically this function has been implemented as a traditional analog pll. at sxga and lower resolutions, an analog pll solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, vco ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). as display resolutions and refresh rates have increased, however, the pixel period has decreased. an xga pixel at a 60hz refresh rate has 15.4ns to change and settle to its new value. but at uxga 75hz, the pixel period is 4.9ns. most consumer graphics cards spend most of that time slewing to the new pixel value. the pixel may settle to its final value with 1ns or less before it begins sl ewing to the next pixel. in many cases it never settles at all. so precision, low-jitter sampling is a fundamental requ irement at these speeds, and a difficult one for an analog pll to meet. the x98027's dpll has less than 250ps of jitter, peak to peak, and independent of the pixel rate. the dpll generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point. the crystal-locked nco inside the dpll completely eliminates drift due to char ge pump leakage, so there is inherently no frequency or phase change across a line. an intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10mhz or higher) to qxga 60hz (275mhz). the dpll eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. automatic black level compensation (ablc?) and gain control traditional video afes have an of fset dac prior to the adc, to both correct for offsets on the incoming video signals and add/subtract an offset for us er ?brightness control?. this solution is adequate, but it plac es significant requirements on the system's firm ware, which must ex ecute a loop that detects the black portion of the signal and then servos the offset dacs until that offset is nulled (or produces the desired adc output code). once this has been accomplished, the offset (both the offset in the afe and the offset of the video card generating the signal) is subject to drift - the temperature inside a monitor or projector can 0x1b power control (0x00) 0 red power-down 0 = red adc operational (default) 1 = red adc powered down 1 green power-down 0 = green adc operational (default) 1 = green adc powered down 2blue power-down 0 = blue adc operational (default) 1 = blue adc powered down 3pll power-down 0 = pll operational (default) 1 = pll powered down 7:4 reserved set to 0 0x1c reserved (0x47) 7:0 reserved set to 0x49 for best performance with ntsc and pal video 0x23 dc restore clamp (0x08) 3:0 reserved set to 1000 6:4 dc restore clamp impedance dc restore clamp's on resistance. shared for all three channels 0: infinite (clamp disconnected) (default) 1: 1600 2: 800 3: 533 4: 400 5: 320 6: 267 7: 228 7 reserved set to 0 0x2b crystal compensation (0x14) 7:0 xtalcomp see table 8 on page 25. register listing (continued) address register (default value) bit(s) function name description x98027
16 fn8221.0 may 26, 2005 easily change 50c between power-on/offset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment have reached steady state. offset can drift significant ly over 50c, reducing image quality and requiring that th e user do a manual calibration once the monitor has warmed up. in addition to drift, many afes exhibit interaction between the offset and gain controls. when the gain is changed, the magnitude of the offset is changed as well. this again increases the complexity of t he firmware as it tries to optimize gain and offset sett ings for a given video input signal. instead of adjusting just the offset, then the gain, both have to be adjusted interactively until the desired adc output is reached. the x98027 simplifies offset and gain adjustment and completely eliminates offset drift using its automatic black level compensation (ablc?) function. ablc? monitors the black level and continuously adjusts the x98027's 10 bit offset dacs to null out the offset. any offset, whether due to the video source or the x98027's analog amplifiers, is eliminated with 10 bit (1/4 of an 8 bit adc lsb) accuracy. any drift is compensated for well before it can have a visible effect. manual offset adjustment control is still available - an 8 bit register allows the firmware to adjust the offset 64 codes in exactly 1 adc lsb increments. and gain is now completely independent of offset - adjusting the gain no longer affects the offset, so there is no longer a need to program the firmware to cope wit h interactive offset and gain controls. finally, there should be no concerns over ablc? itself introducing visible artifacts; it doesn't. ablc? operates at a very low frequency, changing the offset in 1/4 lsb increments, so it doesn't cause visible brightness fluctuations. and once ablc? is locked, if the offset doesn't drift, the dacs won't change. if desired, ablc? can be disabled, allowing the firmware to work in the traditional way, with 10 bit offset dacs und er the firmware's control. gain and offset control to simplify image optimization algorithms, the x98027 features fully-independent gain and offset adjustment. changing the gain does not affect the dc offset, and the weight of an offset dac lsb does not vary depending on the gain setting. the full-scale gain is set in the three 8-bit registers (0x06- 0x08). the x98027 can accept input signals with amplitudes ranging from 0.35v p-p to 1.4v p-p . the offset controls shift t he entire rgb input range, changing the input image brightness. three separate registers provide independent c ontrol of the r, g, and b channels. their nominal setting is 0x80, which forces the adc to output code 0x00 (or 0x80 for u and v channels in yuv mode) during the back porch period when ablc? is enabled. functional description inputs the x98027 digitizes analog video inputs in both rgb and component (ypbpr) formats, with or without embedded sync (sog). rgb inputs for rgb inputs, the black/blank levels are identical and equal to 0v. the range for each color is typically 0v to 0.7v from black to white. hsync and vsync are separate signals. component yuv inputs in addition to rgb and rgb with sog, the x98027 has an option that is compatible with the component ypbpr and ycbcr video inputs typically generated by dvd players. while the x98027 digitizes signals in these color spaces, it does not perform color space conversion; if it digitizes an rgb signal, it outputs digital rgb, while if it digitizes a ypbpr signal, it outputs digital ypbpr. for simplicity?s sake we will call these non-rgb signals yuv. the luminance (y) signal is applied to the green channel and is processed in a manner identical to the green input with sog described previously. the color difference signals u and v are bipolar and swing both above and below the black level. when the yuv mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x80. setting confi guration register 0x05[2] = 1 enables the yuv signal processing mode of operation. the x98027 can optionally decimate the incoming data to provide a 4:2:2 out put stream (configuration register 0x18[4] = 1) as shown in table 2. table 1. yuv mapping (4:4:4) input signal x98027 input channel x98027 output assignment output signal y green green y 0 y 1 y 2 y 3 u blue blue u 0 u 1 u 2 u 3 vredredv 0 v 1 v 2 v 3 table 2. yuv mapping (4:2:2) input signal x98027 input channel x98027 output assignment output signal y green green y 0 y 1 y 2 y 3 u blue blue driven low vredredu 0 v 1 u 2 v 3 x98027
17 fn8221.0 may 26, 2005 input coupling inputs can be either ac-coupled (default) or dc-coupled (see register 0x05[1]). ac coupling is usually preferred since it allows video signals with substantial dc offsets to be accurately digitized. the x98027 provides a complete internal dc-restore function, including the dc restore clamp (see figure 7) and programm able clamp timing (registers 0x14, 0x15, 0x16, and 0x23). when ac-coupled, the dc restore clamp is applied every line, a programmable number of pixels after the trailing edge of hsync. if register 0x05[5] = 0 (the default), the clamp will not be applied while the dpll is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or macrovision signals. after the trailing edge of hsync, the dc restore clamp is turned on after the number of pixels specified in the dc restore and ablc? starting pixel registers (0x14 and 0x15) has been reached. the clamp is applied for the number of pixels specified by the dc restore clamp width register (0x16). the clamp can be applied to the back porch of the video, or to the front porch (by increasing the dc restore and ablc? starting pixel registers so all the active video pixels are skipped). if dc-coupled operation is desired, the input to the adc will be the difference between the input signal (r in 1, for example) and that channel?s ground reference (rgb gnd 1 in that example). sog for component yuv signals, the sync signal is embedded on the y channel?s video, whic h is connected to the green input, hence the name sog (sync on green). the horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. the sync tip level is typically 0.3v below the video black level. to minimize the loading on the green channel, the sog input for each of the green channels should be ac-coupled to the x98027 through a series combination of a 10nf capacitor and a 500 resistor. inside the x98027, a window comparator compares the sog signal with an internal 4 bit programmable threshold level reference ranging from 0mv to 300mv below the minimum sync level. the sog threshold level, hysteresis, and low-pass filter is programmed via register 0x04. if the sync-on-green function is not needed, the sog in pin(s) may be left unconnected. r(gb) in 1 v clamp v in + v in dc restore clamp dac vga1 clamp generation dc restoration automatic black level compensation (ablc) loop bandwidth control offset control registers 8 bit adc offset adc to output formatter fixed offset fixed offset 0x00 ablc ablc ablc 10 10 10 8 8 8 8 8 pga to ablc block input bandwidth vga2 r(gb) gnd 1 r(gb) in 2 r(gb) gnd 2 figure 7. video flow (including ablc?) x98027
18 fn8221.0 may 26, 2005 sync processing the x98027 can process sync signals from 3 different sources: discrete hsync and vsync, composite sync on the hsync input, or composite sync from a sync-on-green (sog) signal embedded on the green video input. the x98027 has sync activity detect functions to help the firmware determine which sync source is available. pga the x98027?s programmable gain amplifier (pga) has a nominal gain range from 0.5v/v (-6db) to 2.0v/v (+6db). the transfer function is: where gaincode is the value in the gain register for that particular color. note that for a gain of 1 v/v for gaincode should be 85 (0x55). this is a different center value than the 128 (0x80) value used by some other afes, so the firmware should take this into account when adjusting gains. the pgas are updated by the internal clamp signal once per line. in normal operation this means that there is a maximum delay of one hsync period between a write to a gain register for a particular color and the corresponding change in that channel?s actual pga gain. if there is no regular hsync/sog source, or if the external clamp option is enabled (register 0x13[5:4]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the gain register to update the pga. this is not an issue in normal operation with rgb and yuv signals. bandwidth and peaking control register 0x0d[3:1] controls a low pass filter allowing the input bandwidth to be adjusted with three bit resolution between its default value (0x0e = 780mhz) and its minimum bandwidth (0x00, for 100mhz). typically the higher the resolution, the higher the desired input bandwidth. to minimize noise, video signals should be digitized with the minimum bandwidth setting that passes sharp edges. 0: vga1 0x05[0] 1: vga2 hsync in 1 hsync1 slicer 0x03[2:0] vsync in 1 sog in 1 hsync2 slicer 0x03[6:4] hsync in vsync in activity 0x01[6:0] & polarity 0x02[5:0] detect hsync in 2 vsync in 2 sog in 2 sync splitter pll 0x0e through 0x13 hsync out vsync out coast generation 0x11, 0x12, 0x13[2] xtal in xtal out 0: 1 0x13 [6] 1: 2 2 xtalclock out output formatter 0x18, 0x19, 0x1a pixel data from afe 24 r p [7:0] r s [7:0] g p [7:0] g s [7:0] b p [7:0] b s [7:0] dataclk hs out vs out sog in sog slicer 0x1c sog slicer 0x1c 00, 10, 11: hsync in 0x05[4:3] 01: sog in 1: sync spltr 0x05[3] 0: vsync in clockinv in hs pixclk csync source sync type vsync dataclk figure 8. sync flow gain v v --- - ?? ?? 0.5 gaincode 170 ----------------------------- + = x98027
19 fn8221.0 may 26, 2005 table 3 shows the corner frequency for different register settings. register 0x0d[7:4] controls a programmable zero, allowing high frequencies to be boosted, restoring some of the harmonics lost due to excessive em i filtering, cable losses, etc. this control has a very large range, and can introduce high frequency noise into the image, so it should be used judiciously, or as an advanced user adjustment. table 4 shows the corner frequency of the zero for different peaking register settings. offset dac the x98027 features a 10 bit digital-to-analog converter (dac) to provide extremely fine control over the full channel offset. the dac is placed after the pga to eliminate interaction between the pga (controlling ?contrast?) and the offset dac (controlling ?brightness?). in normal operation, the offset dac is controlled by the ablc? circuit, ensuring that the offset is always reduced to sub-lsb levels (see the following ablc? section for more information). when ablc? is enabled, the offset registers (0x09, 0x0a, 0x0b) control a digital offset added to or subtracted from the out put of the adc. this mode provides the best image quality and eliminates the need for any offset calibration. if desired, ablc? can be disabled (0x17[0]=1) and the offset dac programmed manually, with the 8 most significant bits in registers 0x09, 0x0a, 0x0b, and the 2 least significant bits in register 0x0c[7:2]. the default offset dac range is 127 adc lsbs. setting 0x0c[0]=1 reduces the swing of the offset dac by 50%, making 1 offset dac lsb the weight of 1/8th of an adc lsb. this provides the finest offset control and applies to both ablc? and manual modes. automatic black level compensation (ablc?) ablc is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the adc and servoing the 10 bit analog dac to force those er rors to zero. when ablc is enabled, the user offset control is a digital adder, with 8 bit resolution (see table 5). when the ablc function is enabl ed (0x17[0]=0), the ablc function is executed every line after the trailing edge of hsync. if register 0x05[5] = 0 (the default), the ablc function will not be triggered while the dpll is coasting, preventing any composite sync edges, equalization pulses, or macrovision signals from corrupting the black data and potentially adding a small error in the ablc accumulator. after the trailing edge of hsync, the start of ablc is delayed by the number of pixels specifi ed in registers 0x14 and 0x15. after that delay, the number of pixels specifie d by register 0x17[3:2] are averaged toget her and added to the ablc?s accumulator. the accumulator stores the average black levels for the number of lines specified by register 0x17[6:4], which is then used to generate a 10 bit dac value. the default values provide e xcellent results with offset stability and absolute accuracy better than 1 adc lsb for most input signals. increasing the ablc pixel width or the ablc bandwidth settings decreases the ablc?s absolute dc error further. adc the x98027 features 3 fully differential, 275msps 8 bit adcs. table 3. bandwidth control 0x0d[3:0] value (lsb = ?x? = ?don?t care?) afe bandwidth 000x 100mhz 001x 130mhz 010x 150mhz 011x 180mhz 100x 230mhz 101x 320mhz 110x 480mhz 111x 780mhz table 4. peaking corner frequencies 0x0d[7:4] value zero corner frequency 0x0 peaking disabled 0x1 800mhz 0x2 400mhz 0x3 265mhz 0x4 200mhz 0x5 160mhz 0x6 135mhz 0x7 115mhz 0x8 100mhz 0x9 90mhz 0xa 80mhz 0xb 70mhz 0xc 65mhz 0xd 60mhz 0xe 55mhz 0xf 50mhz x98027
20 fn8221.0 may 26, 2005 clock generation a digital phase lock loop (dpll) is employed to generate the pixel clock frequency. the hsync input and the external xtal provide a reference frequency to the pll. the pll then generates the pixel clock frequency that is equal to the incoming hsync frequency times the htotal value programmed into registers 0x0e and 0x0f. the stability of the clock is very important and correlates directly with the quality of the image. during each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. at higher frequencies, the pixel time transitions at a faster rate, which makes the stable pixel time even smaller. any jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately. sampling phase the x98027 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. the sampling phase register is 0x10. hsync slicer to further minimize jitter, the hsync inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mv steps with 240mv of hysteresis, and a subsequent digita l glitch filter that ignores any hsync transitions within 100ns of the initial transition. this processing greatly increases the afe?s rejection of ringing and reflections on the hsync line and allows the afe to perform well even with pathological hsync signals. voltages given above and in the hsync slicer register description are with respect to a 3.3v sync signal at the hsync in input pin. to achieve 5v compatibility, a 680 series resistor should be placed between the hsync source and the hsync in input pin. relative to a 5v input, the hysteresis will be 240mv*5v/3.3v = 360mv, and the slicer step size will be 400mv*5v/3.3v = 600mv per step. the best hsync slicer threshold is generally 800mv (001b) when locking on the rising edge of an hsync signal, or 2.4v (110b) when locking on the falling edge. sog slicer the sog input has programmable threshold, 40mv of hysteresis, and an optional low pass filter than can be used to remove high frequency video spikes (generated by overzealous video peaking in a dvd player, for example) that can cause false sog trig gers. the sog threshold sets the comparator threshold relative to the sync tip (the bottom of the sog pulse). a good def ault sog slicer threshold setting is 0x16 (hysteresis and low pass filter enabled, threshold lowered slightly to accommodate weak sync tips). sync status and polarity detection the sync status register (0 x01) and the sync polarity register (0x02) continuously monitor all 6 sync inputs (vsync in , hsync in , and sog in for each of 2 channels) and report their status. howeve r, accurate sync activity detection is always a challenge. noise and repetitive video patterns on the green channel may look like sog activity when there actually is no sog signal, while non-standard sog signals and trilevel sync signals may have amplitudes below the default sog slicer levels and not be easily detected. as a consequence, not all of the activity detect bits in the x980xx are correct under all conditions. table 6 shows how to use the sync status register (0x01) to identify the presence of and type of a sync source. the firmware should go through the table in the order shown, stopping at the first entry that matches the activity indicators in the sync status register. final validation of composite sync sources (sog or composite sync on hsync) should be done by setting the input configuration register (0x05) to the composite sync source determined by this table, and confirming that the csync detect bit is set. the accuracy of the trilevel sync detect bit can be increased by multiple reads of the tril evel sync detect bit. see the trilevel sync detect section for more details. for best sog operation, the so g low pass filter (register 0x04[4]) should always be enabled to reject the high frequency peaking often seen on video signals. table 5. offset dac range and offset dac adjustment offset dac range 0x0c[0] 10 bit offset dac resolution ablc? 0x17[0] user offset control resolution using registers 0x09 - 0x0b only (8 bit offset control) user offset control resolution using registers 0x09 - 0x0b and 0x0c[7:2] (10 bit offset control) 0 0.25 adc lsbs (0.68mv) 0 (ablc on) 1 adc lsb (digital offset control) n/a 1 0.125 adc lsbs (0.34mv) 0 (ablc on) 1 adc lsb (digital offset control) n/a 0 0.25 adc lsbs (0.68mv) 1 (ablc off) 1.0 adc lsb (analog offset control) 0.25 adc lsb (analog offset control) 1 0.125 adc lsbs (0.34mv) 1 (ablc off) 0.5 adc lsb (analog offset control) 0.125 adc lsb (analog offset control) x98027
21 fn8221.0 may 26, 2005 hsync and vsync activity detect activity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the sog activity bit is also set. sog activity detect the sog activity detect bit moni tors the output of the sog slicer, looking for 64 consecutive pulses with the same period and duty cycle. if there is no signal on the green (or y) channel, the sog slicer will clamp the video to a dc level and will reject any sporadic noise. there should be no false positive sog detects if there is no video on green (or y). if there is video on green (or y) with no valid sog signal, the sog activity detect bit may sometimes report false positives (it will detect sog when no sog is actually present). this is due to t he presence of video with a repetitive pattern that create s a waveform si milar to sog. for example, the desktop of a pc operating system is black during the front porch, horizonta l sync, and back porch, then increases to a larger value for the visible portion of the screen. this creates a re petitive video waveform very similar to sog that may falsely trigger the sog activity detect bit. however, in these cases where there is active video without sog, the sync information will be provided either as separate h and v sync on hsync in and vsync in , or composite sync on hsync in . hsync in and vsync in should therefore be used to qualify sog. the sog active bit should only be considered valid if hsync activity detect = 0. note: some pattern generators can output hsync and sog simultaneously, in which case both the hsync and the sog activity bits will be set, and valid. even in this case, however, the monitor should still choose hsync over sog. trilevel sync detect unlike sog detect, the trilevel sync detect function does not check for 64 consecutive tril evel pulses in a row, and is therefore less robust than the sog detect function. it will report false positives for sog-less video for the same reasons the sog activity detect does, and should therefore be qualified with both hsync and sog. trilevel sync detect should only be considered valid if hsync activity detect = 0 and sog activity detect = 1. if there is a sog signal, the trilevel detect bit will operate correctly for standard trileve l sync levels (600mvp-p). in some real-world situations, the peak-to-peak sync amplitude may be significantly smaller, sometimes 300mvp-p or less. in these cases the sync slicer will continue to operate correctly, but the trilevel detect bit may not be set. trilevel detection accuracy can be enhanced by polling the trilevel bit multiple times. if hsync is inactive, sog is present, and the trilevel sync detect bit is read as a 1, there is a high likelihood there is trilevel sync. csync present if a composite sync source (either csync on hsync or sog) is selected through bits 3 and 4 of register 0x05, the csync present bit in register 0x01 should be set. csync present detects the presence of a low frequency, repetitive signal inside hsync, which indicates a vsync signal. the csync present bit should be used to confirm that the signal being received is a reliable composite sync source. sync output signals the x98027 has 2 pairs of hsync and vsync output signals, hsync out and vsync out , and hs out and vs out . hsync out and vsync out are buffered versions of the incoming sync signals; no synchronization is done. these signals should be used for mode detection. hs out and vs out are generated by the x98027?s logic and are synchronized to the output dataclk and the digital pixel data on the output databus. hs out is used to signal the start of a new line of digital data. vs out is not needed in most applications. both hsync out and vsync out (including the sync separator function) remain acti ve in power-down mode. this allows them to be used in c onjunction with the sync status registers to detect valid video without powering up the x98027. table 6. sync source detection table hsync detect vsync detect sog detect trilevel detect result 1 1 x x sync is on hsync and vsync 1 0 x x sync is composite sync on hsync. set i nput configuration register to csync on hsync and confirm that csync detect bit is set. 0 0 1 0 sync is composite sync on sog. it is possible that trilevel sync is present but amplitude is too low to set trilevel det ect bit. use video mode table to de termine if this video mode is likely to have trilevel sync, and set clamp st art, width values appropriately if it is. 0 0 1 1 sync is composite sync on sog. sync is likely to be trilevel. 0 0 0 x no valid sync sources on any input. x98027
22 fn8221.0 may 26, 2005 hsync out hsync out is an unmodified, buffered version of the incoming hsync in or sog in signal of the selected channel, with the incoming signal?s period, polarity, and width to aid in mode detection. hsync out will be the same format as the incoming sync signal: either horizontal or composite sync. if a sog in put is selected, hsync out will output the entire sog signal, including the vsync portion, pre-/post-equalization pulses if present, and macrovision pulses if present. hsync out remains active when the x98027 is in power-down mode. hsync out is generally used for mode detection. vsync out vsync out is an unmodified, buffered version of the incoming vsync in signal of the selected channel, with the original vsync period, polarity, and width to aid in mode detection. if a sog input is selected, this signal will output the vsync signal extracted by the x98027?s sync slicer. extracted vsync will be the width of the embedded vsync pulse plus pre- and post-equalization pulses (if present). macrovision pulses from an ntsc dvd source will lengthen the width of the vsync pulse. macrovision pulses from other sources (pal dvd or videotape) may appear as a second vsync pulse encompassing the width of the macrovision. see the macrovision section for more information. vsync out (including the sync separator function) remains active in power-down mode. vsync out is generally used for mode detectio n, start of field detection, and even/odd field detection. hs out hs out is generated by the x98027?s control logic and is synchronized to the output dataclk and the digital pixel data on the output databus. its trailing edge is aligned with pixel 0. its width, in units of pixels, is determined by register 0x19, and its polarity is determi ned by register 0x18[7]. as the width is increased, the trailing edge stays aligned with pixel 0, while the leading edge is moved backwards in time relative to pixel 0. hs out is used by the scaler to signal the start of a new line of pixels. the hsout width register (0x19) controls the width of the hs out pulse. the pulse width is nominally 1 pixel clock period times the value in this register. in the 48 bit output mode (register 0x18[0] = 1), or the yuv input mode (register 0x05[2] = 1), the hs out width is incremented in 2 pixel clock (1 dataclk) increments (see table 7). vs out vs out is generated by the x98027?s control logic and is synchronized to the output dataclk and the digital pixel data on the output databus. its leading and trailing edges are aligned with pixel 7 (8 pixels after hsync trailing edge). its width, in units of lines, is equal to the width of the incoming vsync (see the vsync out description). its polarity is determined by register 0x18[6]. this output is not needed in most applications. macrovision the x98027 will synchronize to and digitize macrovision- encoded yuv video if the source is an ntsc dvd. macrovision from pal dvd, or from all video tape sources, is incompatible with the sync slicer, requiring that the macrovision pulses either be st ripped from the video prior to the sog in input, or an external coast signal be generated and applied to the clkinv pin that will coast the x98027?s pll during the vsync and macrovision period. standby mode the x98027 can be placed into a low power standby mode by writing a 0x0f to register 0x1b, powering down the triple adcs, the dpll, and most of the internal clocks. to allow input monitoring and mode detection during power- down, the following blocks remain active: ? serial interface (including the crystal oscillator) to enable register read/write activity ? activity and polarity detect functions (registers 0x01 and 0x02) ? the hsync out and vsync out pins (for mode detection) table 7. hs out width register 0x19 value hs out width (pixel clocks) 24 bit mode, rgb 24 bit mode, yuv all 48 bit modes 0010 1110 2232 3332 4454 5554 6676 7776 x98027
23 fn8221.0 may 26, 2005 crystal oscillator an external 23mhz to 27mhz crystal supplies the low-jitter reference clock to the dpll. the absolute frequency of this crystal within this range is unimp ortant, as is the crystal?s temperature coefficient, allowing use of less expensive, lower-grade crystals. see table 8 for additional crystal considerations. emi considerations there are two possible sources of emi on the x98027: ? crystal oscillator. the emi from the crystal oscillator is negligible. this is due to an amplitude-regulated, low voltage sine wave oscillator ci rcuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. the crystal oscillator is not a significant source of emi. ? digital output switching. this is the largest potential source of emi. however, the emi is determined by the pcb+ layout and the loading on the databus. the way to control this is to put series re sistors on the output of all the digital pins. these resistor values should be adjusted to optimize signal quality on the bus. intersil recommends starting with 22 and adjusting as necessary for the particular pcb layout and device loading. recommendations for minimizing emi are: ? minimize the databus trace length ? minimize the databus capacitive loading. if emi is a problem in the fina l design, increase the value of the digital output series resistors to reduce slew rates on the bus. this can only be done as long as the scaler?s setup and hold timing requirements continue to be met. alternate pixel sampling two x98027s (afe a and afe b ) may be used simultaneously to achieve effective sample rates greater than 275mhz. each afe is programmed with an htotal value equal to one-half of the total number of pixels in a line. the clockinv in pin for afe a is tied to ground, afe b is tied to v d . both afes are otherwise programmed identically, though some minor phase adjustment may be needed to compensate for any propagation delay mismatch between the two afes. the clockinv in setting shifts the phase of afe b by 180 degrees from afe a . afe a now samples the even pixels on the rising edge of its dataclk, while afe b samples the odd pixels on the rising edge of its clock. with each afe in 24 bit mode, two 24 bit data streams are generated (figure 9). with both afes configured for 48 bit mode, a 96 bit datastream is generated (figure 10). in both cases, afe a and afe b are on different dataclk domains. in 24 bit mode, the data from each afe must be latched on the rising edge of that afe?s dataclk. in 48 bit mode, the frequencies are low enough that the rising edge of afe b can be used to capture both afe b and afe a data. hsync in (to a and b) dataclk (a) data (a) hs out (a) dataclk (b) data (b) hs out (b) dpll lock edge ? dataclk delay clkinv in (a) = gnd d clkinv in (b) = v d d 0 d 2 d 3 d n d 1 d n-3 d n-1 d n-2 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 p 10 p 11 p 12 p n-3 p n-2 p n-1 p n analog video in (to a and b) figure 9. alternate pixel sampling (24 bit mode) x98027
24 fn8221.0 may 26, 2005 . initialization the x98027 initializes with default register settings for an ac-coupled, rgb input on the vga1 channel, with a 24 bit output. the following registers should be written to fully enable the chip: ? register 0x1c should be set to 0x49 to improve dpll performance in video modes ? register 0x23 should be set to 0x78 to enable the dc restore function ? write the correct crystal compensation value to register 0x2b (see below). power dissipation at qxga speeds because of the very high speed of the x98027, power consumption is a concern. there are several things that can be done to reduce power consumption: internal clock frequency the internal clock frequencies need to be tightly controlled to minimize power consumption. register 0x2b should be set to 1 + the integer portion of (2*fpixelclockmax/fcrystal ). for example, if the maximum pixel clock is 263mhz, and the crystal frequency is 24mhz, then register 0x2b should be set to 1 + int(2*263/24) = 1 + int(21.917) = 1 + 21 = 22 = 0x16. the following table illustrates the compensation va lues required to operate the x98027 at its maximum speed of 275mhz. if lower maximum pixel clock frequencies are needed, using the formula above will minimize power consumption. hsync in (to a and b) pixelclk (a) (internal) data pri (a) hs out (a) dpll lock edge ? pixelclk = ? dataclk delay clkinv in (a) = gnd d p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 p 10 p 11 p 12 p n-3 p n-2 p n-1 p n analog video in (to a and b) data sec (a) dataclk (a) d 0 d 2 d n-3 d n-1 clkinv in (b) = gnd d d 1 d 3 d n-2 d n pixelclk (b) (internal) data pri (b) hs out (b) data sec (b) dataclk (b) figure 10. alternate pixel sampling (48 bit mode) x98027
25 fn8221.0 may 26, 2005 internal voltage regulator the x98027 features a 3.3v to 1.9v voltage regulator (pins 64 and 65). this regulator typically sources up to 100ma at 1.9v, dissipating up to 140mw in heat. providing an external, clean 1.8v supply to the vcore, vpll, and vcoreadc will substantially reduce power dissipation ? buffering digital outputs switching 48 data output bits at a 275mhz/2 rate consumes a lot of current. the higher the capacitance on the external databus, the higher the switching current. to minimize current consumption inside the x98027, data buffers such as the sn64avc16827 should be placed between the x98027?s data outputs and the external databus. for bus capacitances of 15pf or lower, this is highly recommended. for bus capacitances greater than 15pf, this is mandatory! reset the x98027 has a power-on reset (por) function that resets the chip to its default state when power is initially applied, including resetting all the registers to their default settings as described in the register listing. the external reset pin duplicates the reset function of the por without having to cycle the power supplies. the reset pin does not need to be used in normal operation and can be tied high. rare csync considerations intersil has discovered one anomaly in its sync separator function. if the csync signal shown in figure 11 is present on the hsync input, and the sync source is set to csync on hsync, hs out may sporadically lock to the wrong edge of hsync in . this will cause the hs out to have the wrong position relative to pixel 0, resulting in the image shifting left or right by the width of the hsync in signal for about 1 second before it corrects itself. this only happens with the exact waveshape shown in figure 11. if the polarity of the sync signal is inverted from that shown in figure 11, the problem will not occur. if there are any serrations during the vsync period, the problem will not occur. the problem also will not occur if the sync signal is on the sog input. this is a rarely used composite sync format; in most applications it will never be encountered. however if this csync waveform must be supported, there is a simple applications solution using an xor gate. the output of the xor gate is connected to the hsync in input of the x98027. one of the xor inputs is connected to the hsync/csync source, and the other input is connected to a general purpose i/o. for all sync sources except the csync shown in figure 11, the input connected to the gpio should be driven low. if the system microcontroller detects a mode corresponding to the sync type and polarity shown in figure 11, it should drive the gpio pin high. this will invert the csync signal seen by the x98027 and prevent any spontaneous image shifting. x98027 serial communication overview the x98027 uses a 2 wire serial bus for communication with its host. scl is the serial clock line, driven by the host, and sda is the serial data line, which can be driven by all devices on the bus. sda is open drain to allow multiple devices to share the same bus simultaneously. table 8. x98027 crystal compensation crystal frequency range (mhz) register 0x2b value value (decimal) hex 23 - 23.9 24 0x18 23.9 - 25 23 0x17 25.0 - 26.2 22 0x16 26.2 - 27 21 0x15 figure 11. csync on hsync that may cause sporadic image shifts t 1 t 2 hsync in conditions required: negative polarity vsync, with no serrations, and t 1 = t 2 x98027
26 fn8221.0 may 26, 2005 communication is accomplished in three steps: 1. the host selects the x98027 it wishes to communicate with. 2. the host writes the initial x98027 configuration register address it wishes to write to or read from. 3. the host writes to or reads from the x98027?s configuration register. the x98027?s internal address pointer auto increments, so to read registers 0x00 through 0x1b, for example, one would write 0x00 in step 2, then repeat step 3 28 times, with each read returning the next register value. the x98027 has a 7 bit address on the serial bus. the upper 6 bits are permanently set to 100110, with the lower bit determined by the state of pin 48. this allows 2 x98027s to be independently controlled while sharing the same bus. the bus is nominally inactive, with sda and scl high. communication begins when the host issues a start command by taking sda low while scl is high (figure 12). the x98027 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. the host then transmits the 7 bit serial address plus a r/w bit, indicating if the next transaction will be a read (r/w = 1) or a write (r/w = 0). if the address transmitted matches that of any device on the bus, that device must respond with an acknowledge (figure 13). once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. communication with the selected device in t he selected direction (read or write) is ended by a stop command, where sda rises while scl is high (figure 12), or a second start command, which is commonly used to reverse data direction without relinquishing the bus. data on the serial bus must be valid for the entire time scl is high (figure 14). to achieve this, data being written to the x98027 is latched on a delayed version of the rising edge of scl. scl is delayed and deglitched inside the x98027 for 3 crystal clock periods (120ns for a 25mhz crystal) to eliminate spurious clock pulses that could disrupt serial communication. when the contents of the x98027 are being read, the sda line is updated afte r the falling edge of scl, delayed and deglitched in the same manner. configuration register write figure 15 shows two views of the steps necessary to write one or more words to the configuration register. configuration register read figure 16 shows two views of the steps necessary to read one or more words from the configuration register. scl sda start stop figure 12. valid start and stop conditions scl from host data output from transmitter data output from receiver 8 1 9 start acknowledge figure 13. acknowledge response from receiver x98027
27 fn8221.0 may 26, 2005 scl sda data stable data change data stable figure 14. valid data changes on the sda bus x98027 serial bus address write this is the 7 bit address of the x98027 on the 2 wire bus. the address is 0x4c if pin 48 is low, 0x 4d if pin 48 is high. shift this value to left when adding the r/w bit d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 x98027 register data write(s) this is the data to be written to the x98027?s configuration register. note: the x98027?s configuration register?s address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the configuration register. a6 a5 1 00 0 1 a (pin 48) 0 1 r/w x98027 register address write this is the address of the x98027? s configuration register that the following byte will be written to. x98027 serial bus address start command stop command (repeat if desired) signals the beginning of serial i/o signals the ending of serial i/o s t a r t s t o p data write* register address serial bus address a c k aaaaaaaa a c k dddddddd a c k 100110a0 * the data write step may be repeated to write to the x98027?s configuration register sequentia lly, beginning at the register address written in the previous step. sda bus signals from the x98027 signals from the host figure 15. configuration register write x98027
28 fn8221.0 may 26, 2005 x98027 serial bus address write this is the 7 bit address of the x98027 on the 2 wire bus. the address is 0x4c if pin 48 is low, 0x4d if pin 48 is high. r/w = 0, indicating next transaction will be a write. a0 a7 a2 a4 a3 a1 a6 a5 1 00 0 1 a (pin 48) 0 1 r/w x98027 register address write this sets the initial address of the x98027?s configuration register for subsequent reading x98027 serial bus address start command signals the beginning of serial i/o x98027 serial bus address write this is the 7 bit address of the x98027 on the 2 wire bus. the address is 0x4c if pin 48 is low, 0x4d if pin 48 is high. r/w = 1, indicating next transaction(s) will be a read. d7 d6 d5 d2 d4 d3 d1 d0 x98027 register data read(s) this is the data read from the x98027?s configuration register. note: the x98027?s configuration register?s address pointer auto increments after each data read: repeat this step to read multiple sequential bytes of data from the configuration register. 1 00 0 1 a (pin 48) 1 1 r/w x98027 serial bus address start command stop command (repeat if desired) ends the previous transaction and starts a new one signals the ending of serial i/o s t a r t s t o p data read* sda bus signals from the x98027 signals from the host register address serial bus address a c k aaaaaaaa a c k dddddddd a c k 100110a0 * the data read step may be repeated to read from the x98027?s configuration register sequentially, beginning at the register address written in the two steps previous. r e s t a r t serial bus address a c k 100110a1 figure 16. configuration register read x98027
29 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8221.0 may 26, 2005 128-lead metric quad flat pack (mqfp) package type l all dimensions in mm. x98027

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